Random access memory (RAM) is an indispensable component in electronic devices and systems. There are two main types of RAM—dynamic RAM (DRAM) and static RAM (SRAM). DRAM is the most common type of RAM used in computer systems. Its advantage over SRAM is its structural simplicity. Whereas a DRAM memory cell requires only a single transistor and capacitor, an SRAM memory cell requires six transistors. For this reason SRAM technology is not well-suited for high-capacity, low-cost applications such as personal computer (PC) memory. Nevertheless, SRAM technology has a number of benefits over DRAM technology. First, SRAM is faster (i.e., can be read and written to more quickly than DRAM). Second, SRAM cells do not need to be refreshed and are capable of reliably maintaining their logic state, so long as power is continuously supplied to the cell. By contrasts, DRAM cells must be periodically refreshed to ensure that the logic state stored by the cell is properly maintained. Sensing the DRAM cell, for example to refresh the cell, can be problematic in some applications since the refresh process temporarily disrupts the current logic state stored in the SRAM cell. For these reasons, SRAM technology is preferred over DRAM technology in some applications.
FIG. 1A is a schematic drawing of a conventional SRAM cell 100. The SRAM cell 100 comprises a latch 102, which includes two cross-coupled inverters 104, 106, and two access transistors 108, 110, which serve to control access to the latch 102 during read and write operations. FIG. 1B shows the SRAM cell 100 in FIG. 1A at a transistor level. The SRAM cell has three different states: a standby state, a read state, and a write state. When in the standby state, the access transistors 108, 110 are OFF and decouple the latch 102 from the bit lines, BL and BL. The two cross-coupled inverters 104, 106 (comprising transistors 112, 114 and 116, 118, respectively) continue to reinforce each other.
The SRAM cell 100 is read as follows. Assume, for example, that the SRAM cell 100 is storing a logic “1” (logic “1” appears at terminal Q and logic “0” appears at Q). The read cycle commences by precharging both bit lines, BL and BL, to a logic “1” level. The word line, WL, is then asserted, thereby enabling both access transistors 108, 110. The Q and Q logic levels are transferred to the bit lines, BL and BL, by leaving BL at its precharged value and discharging BL through transistors 108 and 118 to a logic “0”. At the same time, transistors 110 and 112 pull BL up to the supply voltage, VDD, thereby pulling BL to a logic “1”. If the SRAM cell 100 is configured to store a logic “0” at the start of the read cycle, the reverse process is performed, i.e., BL is pulled up to a logic “1” and BL is pulled down to a logic “0”.
The SRAM cell 100 is written to by first applying the logic value to be written to the bit lines BL and BL. For example to write a logic “0” to the cell 100, a logic “0” is asserted on BL and a logic “1” is asserted on BL. This causes the latch 102 to change state from a logic “1” to a logic “0”. Then the WL is asserted and the logic value to be written (in this example, a logic “0”) is latched into the latch 102.
While SRAM technology is used in a wide variety of applications, it is a well knows fact that it is susceptible to radiation-induced soft errors. These soft errors (commonly referred to in the art as “single event upsets” (SEUs)), are caused by alpha particles, cosmic rays and nuclear reaction products of terrestrial neutrons and semiconductor material, which impinge on the transistors of the latch 102 and cause the latch 102 to unexpectedly and undesirably flip logic states. SEUs can lead to erroneous data and even system crashes. In some circumstances, SEUs may be corrected by rewriting correct data in place of erroneous data, e.g., by using sophisticated error correction circuitry (ECC). However, in other circumstances, it may be impossible to determine the correct data, or to discover that an error has even occurred.
On-chip memory such as SRAM is considered to be the most sensitive circuit component to SEUs, which are measured by what is known as the “soft error rate” (SER), since it typically occupies a substantial portion of the chip area, and since it usually has the lowest critical charge Qcrit (i.e., the minimum amount of charge required to cause an upset). For this reason, ECC has largely been directed at correcting errors in memory portions of a chip to reduce the SER. While ECC has been shown to be effective at reducing memory SER, technology scaling trends indicate that logic SER could limit the benefit of ECC in the near future. This limitation is compounded by the fact that ECC tends to consume a large portion of semiconductor chip area, which makes it difficult to ensure all parts of the chip are immune to SEUs.
Aside from the deleterious effects on SER resulting from technology scaling, in some applications ECC does not provide a suitable or efficient means for reducing SER. For example, SRAM technology is often used to configure programmable logic devices, such as field programmable gate arrays (FPGAs). SRAM cells in an FPGA are used to configure the logic blocks, input/output (I/O) blocks and interconnect structure. Because the functions performed by the FPGA are determined by the logic values of the SRAM configuration memory cells, any error in the SRAM values can affect the intended functionality of the FPGA. Indeed, in an FPGA configured to implement a complex design, it is possible that a single error could render the entire design inoperative. For these reasons, conventional ECC is not considered to be a suitable solution to reducing SER in SRAM-based FPGAs.
The problems and limitations associated with ECC described above have led to alternative approaches to “hardening” latch-based logic and memory cells. For example, U.S. Pat. No. 6,735,110 teaches addressing SEU conditions in FPGAs by inserting transistors or inductors at the input/output nodes of the cross-coupled inverters of the SRAM cell latch. Unfortunately, those approaches are plagued with the disadvantage of large area consumption and cell performance degradation.
What is needed, therefore, are techniques for hardening latch-based circuits and memory cells that: introduce little or no layout penalty, do not adversely affect circuit speed, and are simple and inexpensive to implement in conventional semiconductor manufacturing process flows.